Question

1) Using always statement, write a transparent latch having active high “enable”, and active low “set” and “reset”. The action of reset is to drive the output of the latch to 0.

2) Without using always statement, write a transparent latch having active low “enable”, and active high “set” and “reset”. The action of reset is to drive the output of the latch to 0.

Problem 2.

a) Using two instantiations of the latch you developed in 1(a), implement a DFlipFlop.

b) Write a proper test-bench and stimulus, thoroughly test your D-FlipFlop. Also, show your waveform and describe why your D-FF does what is is designed to do

Answer 1

answer 1 a.)

module d_latch(d,enable,set_n,reset_n,q,q_bar);
input d,enable,set_n,reset_n;//inputs
output reg q,q_bar;//outputs
assign q_bar=~q;
always@(*)// always block
begin
if(!reset_n)// active low reset having highest priority
q=0;
else if(!set_n)// active low set
q=1;
else if(enable)// active high enable
q=d;
else
q=0;
end
endmodule

answer 1 b.)

module d_latch2(d,enable,set,reset,q,q_bar);
input d,enable,set,reset;// inputs
output reg q,q_bar;// outputs
assign q_bar=~q;
initial// initial block until all the statements are finished
begin
forever@(*)// forever block run until $finish is called just like always block
if(reset)// active high reset highest priority
q=0;
else if(set)// active high set
q=1;
else if(enable)// active high enable
q=d;
else
q=0;
end
endmodule

answer 2 a.)

module dff(d,clk,q,q_bar,reset_n,set_n);
input d,clk,reset_n,set_n;
output q,q_bar;
wire q1,q_bar1;
d_latch d2(d,(~clk),set_n,reset_n,q1,q_bar1);// dlatch with enable
d_latch d3(q,(clk),set_n,reset_n,q,q_bar);// dlatch with output cascaded as (q_bar) and enable = enable
endmodule

b.)

testbench:

module test();
reg d,enable,reset_n,set_n;
wire q,q_bar;
  
dff d1(d,enable,q,q_bar,reset_n,set_n);
  
initial
begin
reset_n=0;set_n=0;d=0;enable=0;// both resrt and set active
#2 set_n=1;reset_n=0;// only rset active
#2 set_n=0;reset_n=1;// only set active
#2 set_n=1;reset_n=1;enable=1;d=1;// enable is active with d=1
#2 enable=0;d=0;
#2 enable=1;d=0;
#2 enable=0;
end
initial// waveform generation sing dump file
begin
$dumpfile("dump.vcd");
$dumpvars(2);
end
endmodule

output:

when two d_latches are connected one with enable and another with not enable and their outputs are cascaded.

we see that one of the latches works as a master when enable=0 the l1 latches the value of D and in positive edge, the output is then propagated to the result.

hence only the input value present at the positive edge will be transferred. hence it behaves like a d-ff.

since each of the latches, the input at different states of enable the value latched then propagated. hence only one part of duty cycle is not active for input detection hence inferring flip=flop