Question

IF=250ps, ID=350ps, EX=150ps, MEM=300ps, WB=200ps

 What is the clock cycle time in a pipelined processor?

 What is the total latency of a LOAD instruction in a pipelined and non-pipelined processor?

 If we can split any one of the 5 stages above into 2, which one would you split?

 What is the new cycle time of the pipelined processor?

 What is the new latency for the LOAD instruction for both pipelined and non-pipelined processor?

Answer 1

Ans

1 Ans

For a pipelined processor, the clock cycle is the time

of the pipeline element with the largest latency:

Clock cycle = 350 ps

2 Ans

Pipelined processor takes 5 cycles at 350ps (longest stage) per cycle for total latency of 1750ps

non pipeline :

we can add up stages which would be =250+350+150+300+200 = 1250 ps

3 Ans

We would split the stage with longest latency, ID which is 350 ps

4 Ans

From the 3rd solution: after split the longest stage

The new longest stage, which determines the clock, would be 300 ps

I am very sorry I can't able to answer 5th questions (ad per as HomeworkLib policy)

Thanks for given this opportunity

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