Question

Assume that the following RISC-V code is executed on a pipelined processor with a 5-stage pipeline with full forwarding and a predict-taken branch predictor. Draw the pipeline diagram and report number of clock cycles it takes to execute this sequence of instructions. Note: Result of branch is determined in EXE stage.

Label1:

lw X1, 40(X6)

beq X2 , X3 , Label2 # Taken

add X1 , X6 , X4

Label2:

beq X1 , X2 , Label1 # Not Taken

sw X2 , 20(X4)

and X1 , X1 , X4

Answer 1