Question

16.1. Consider a “one-sided” Si PN idode with N_A= 2.0 × 10¹⁸ cm^-3 and N_D= 4.0 × 10¹⁶ cm^-3.
(a) Evaluate the Fermi level in each region, evaluate V_FB and draw the ideal flat-band diagram.
(b) For V = 0 find the depletion-layer widths w_pand w_nand the electric field E at the junction.
(c) Evaluate the charge stored in the junction, and evaluate the small-signal capacitance, still at V = 0.
(d) Now assume a reverse bias of V = -8.0 V. Find the depletion layer widths, junction electric field, stored charge and small signal capacitance of the diode at this voltage.

16.2. Consider a Si PN diode with N_A= 2.0 × 10¹⁷ cm^-3, N_D= 8.8 × 10¹⁶ cm^-3, and A = 10μm × 10μm. The diode is at room temperature (T = 300 K). Assume that the mobility for electrons is 800 cm²/Vs, the mobility for holes is 400 cm²/Vs, τ_n= 0.2 μs and τ_p= 0.4 μs. Take the Si bandgap to be 1.12 eV.
(a) Calculate the flat-band (or built-in) voltage V_FB (V_bi).
(b) Calculate how much of the built-in electrostatic potential Δφ is accommodated in the P-type and N-type regions, respectively.
(c) Calculate the zero-bias depletion-layer widths in the P and N regions, w_pand w_n.
(d) If we express the diode I(V) characteristic as in (16.24), calculate the value IS.
(e) If the diode is biased forward at a voltage of 0.750 V, evaluate n[P], and p[N], at the appropriate depletion-layer boundary, and evaluate the total current through the diode.
(f) If the diode is reverse biased to V = -5.0 V, evaluate the depletion-layer widths w_pand w_n, and the total depletion layer width

Answer 1