
6.27 using verilog

module Vrmultidec8(
input [2:0] A,
input CS_L,
output [8*4,1] output
);
reg [8*4, 0] output;
always @(CS_L)
begin
if(CS_L) begin
if(A[2] == 1'b0 && A[1] == 1'b0) begin
output <= "BILL";
end else if (A[2] == 1'b0 && A[0] == 1'b0) begin
output <= "MARY";
end else if (A[2] == 1'b0 && A[1] == 1'b1) begin
output <= "JOAN";
end else if (A[2] == 1'b0 && A[0] == 1'b1) begin
output <= "PAUL";
end else if (A[2] == 1'b1 && A[1] == 1'b0) begin
output <= "ANNA";
end else if (A[2] == 1'b1 && A[0] == 1'b0) begin
output <= "FRED";
end else if (A[2] == 1'b0 && A[1] == 1'b1) begin
output <= "ATIF";
end else if (A[1] == 1'b1 && A[0] == 1'b1) begin
output <= "KATE";
end
end
end
endmodule
The module has 2 inputs:
1. A with 3 bits
2. CS_L with 1 bit
The output has 32 bits. This is because there are 4 characters in the output and each character is of 8 bits.
So the size of output = 8*4 = 32;
We are using bit extraction of register to compare with values in table.
Ušing a generate l Denavioral module Vr8to256decb for the same icatin te a test bench Vr8to256dec...