Question

SRAP pr- Vivado 2017. Eile Edit Flow Iools Window Layout Yew HelpQuick Acces Ready VO Planning Flow Navigator V PROJECT MANAGER Cell Properties x Clock Regions ?-OC Package x Device xsrapvhd × Schematic X O Setings Language Templates IP Catalog IPINTEGRATOR Open Block Design Qngl3이 OutVed3이 Generate Block Design SIMULATION R3.0 Run Simulation RTL ANALYSIS n Elaborated Design 白Report Methodology Report DRC Report Noise Schematic Td Console Messages Lg Reports Design Runs Package Pins VO Ports Type here to search 3/13/2018 2. Complete this VHDL to implement fig. 1(b) where L-0 means "shifting like SR4" and L-1 means "parallel load input vector R into 4-bit regsiter Q on positive-edge of clock." entity SR4P library ieee use ieee.std_logic 1164.all; entity SR4P is port InBit,Clock,L: in std_logic; R: in std_logic_vector (3 downto 0); OutVec: out std_logic_vector (3 downto 0)); end SR4P; architecture behavorial of SR4P is signal Q: std-logic-vector (3 downto 0) begin PROCESS (Clock) :="0000".-signal Q is the 4-bit register begin if rising_edge(Clock) then if L-'1' then else Q(2)

Answer 1

library ieee;
use ieee.std_logic_1164.all;

entity SR4P is
   port (   InBit, Clock, L   : in std_logic;
       R       : in std_logic_vector(3 downto 0);
       OutVec       : out std_logic_vector(3 downto 0)
   );
end SR4P;

architecture behavorial of SR4P is

signal Q : std_logic_vector(3 downto 0) := "0000";

begin

process (Clock)

begin

   if rising_edge(Clock) then

       if L = '1' then

           Q <= R;

       else

           Q(3) <= InBit;
           Q(2) <= Q(3);
           Q(1) <= Q(2);
           Q(0) <= Q(1);

       end if;

   end if;

end process;

OutVec <= Q;

end behavorial;

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