1. Compile the following C program using the most effective DLX code, similar to the example given in the class.
int A[200], B[200], C[200];
.....
for(i=0;i<200;i++) A[i]=B[i]+C[i]*5;
Assume array A, B and C each starts at memory location x1000, x2000 and x3000, respectively. You will need to establish each of these addresses in a register (use r1, r2 and r3 for each of the three) before the loop. Also, you need to establish a counter register for “i” (use r4) and initialize it to 0.
1. Compile the following C program using the most effective DLX code, similar to the example give...
Problem: On an ARM processor using big endian format, given the following memory map and [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C, predict [R1] and [R2] and draw the updated memory map after an ARM data transfer instruction is executed in EACH case. (hint: (1) in this map, each memory location is a word long and occupies 4 bytes; also you only need to draw the section of the memory including the changed word and...
Problem: On an ARM processor using big endian format, given the following memory map and [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C, predict [R1] and [R2] and draw the updated memory map after an ARM data transfer instruction is executed in EACH case. (hint: (1) in this map, each memory location is a word long and occupies 4 bytes; also you only need to draw the section of the memory including the changed word and...
help
Question 11 The classic five-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings: • The architecture fully supports forwarding, • Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, • Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism, • Register R4 is initially 200....
The classic five-stage pipeline MIPS architecture is used to execute the code fragments in this problem. Assume the followings: • The architecture fully supports forwarding, • Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle, • Branches are resolved in the third stage of the pipeline and the architecture does not utilize any branch prediction mechanism, • Register R4 is initially 200. L1: lw lw...
Problem: On an ARM processor using big endian format, given the following memory map and [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C, predict [R1] and [R2] and draw the updated memory map after an ARM data transfer instruction is executed in EACH case. (hint: (1) in this map, each memory location is a word long and occupies 4 bytes; also you only need to draw the section of the memory including the changed word and...
Modify the ARMSIM program to do the following: 1) output the square sum of the data 2) output the sum of all negatives and positives separately .text @ Direvtive .global _start @ declare global begining _start: LDR R1,=idx @ content of idx is length of Vec and now R1 is a counter. LDR R1,[R1] @ R1 is now the length of Vec. read inderectly LDR R2,=Vec @ R2 is the address of first element of vector MOV...
2. a)Write the ARM ALP conditional code snippet for the following statements written in C-language. Assume R1 to Rn as06 variables Let R1, R2, R3 contain the starting addresses of arrays X, Y and Z respectively Use Register R4 for variable i. Display appropriate messages. While (i+10) else Z[i] XiYi; b)i Write a program to display a message "This is an examination Question" on the screen using 06 a function sub program Note the following Address of the string to...
A data scientist needs a MIPS assembly-language program for data analysis. He has three arrays of floating-point numbers. Array 'a' is a source array, and 'b' and 'c' are result arrays. Array 'a' contains '2n' floating-point numbers. 'r1' is the address of 'a[0]'. 'r4' is the address of the byte immediately following 'a', i.e., the address of the imaginary element 'a[2n]'. Each of 'b' and 'c' can store 'n' floating-point numbers. 'r2' is the address of 'b[0]'. 'r3' is the...
Question 1. Assume the following C program and You are writing
code using SPIM to implement this program.
Write the results of each of the following in MIPS instructions.
Use registers $t0 - $t7 as needed, Note: int requires 8 bytes
1. Load the contents of dot_prod and
i into registers
2. Load the contents of a[i] and b[i] into
registers
3. Calculate dot_prod + a[i]*b[i] and save the
result into dot_prod
please answer each point from (1,2,3) in separated...
The Fibonacci sequence F is defined as F(1) = F(2) = 1 and for n>= 2, F(n + 1) = F(n) + F(n − 1) i.e., the (n + 1)th value is given by the sum of the nth value and the (n − 1)th value. 1. Write an assembly program typical of RISC machines for computing the kth value F(k), where k is a natural number greater than 2 loaded from a memory location M, and storing the result...