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itby important Q. Disc uss the features of RISC and CISC Architecture. dware implementations Mt &t M2 of the same instruction

Please Solve 1(c).

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Answer #1

1 (C) . before starting the answer of this let us find the average CPI before new implementation

Type CPI PART product
F 5 0.25 1.25
I 2 0.25 0.5
N 2.4 .50 1.2

Total Cpi = 2.95 with 600 MHz clock rate

now we will use the speed up factor to compare which new strategy will be good

Speed up S =\frac{old execution time}{new execution time}

old execution time = 2.95* 1/ (600 *10^-6)

1.) now just modify CPI of F to 2.5 so

Type CPI PART product
F 2.5 0.25 0.625
I 2 0.25 0.5
N 2.4 .50 1.2

New Cpi = 2.325 new clock rate =600

new execution time = 2.325 * 1 / ( 600 * 10^-6)

Speed up S = 2.95 * 600 * 10^-6 / 2.325* 600 * 10^-6 = 1.27

2 .) now just modify CPI of I to 1.2 so

Type CPI PART product
F 5.0 0.25 1.25
I 1.2 0.25 0.3
N 2.4 .50 1.2

New Cpi = 2.75 new clock rate =600

new execution time = 2.75 * 1 / ( 600 * 10^-6)

Speed up S = 2.95 * 600 * 10^-6 / 2.75* 600 * 10^-6 = 1.07

3.) now just update the clock speed so

Type CPI PART product
F 5 0.25 1.25
I 2 0.25 0.5
N 2.4 .50 1.2

New Cpi = 2.95 with 750 MHz clock rate

new execution time = 2.95 * 1 / ( 750 * 10^-6)

Speed up S = 2.95 * 750 * 10^-6 / 2.95* 600 * 10^-6 = 1.25

so considering all the speedups we get largest speed up i.e. S =1.27 for the first approach why?

because in original the F class has largest CPI also the contribution in the CPI by F is 1.25 which is largest so if we anyhow modify this parameter then we may get the best possible result and which is done in the first approach that is why impact of first approach is maximum which leads us to a largest speedup

Also if we consider that in the 3rd approach we got 1.25 speedup which is near to the largest because the speed of all the instructions are increased .

I hope it'll help you so please give positive ratings :))))))))

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