Question

6.(15 points) a)Write VHDL code for the following Soda Dispenser controller. It is a synchronous FSM with an active high Reset signal. b) What type of FSM is? States: Init, Wait, Disp Inputs Enough Outputs d, cl Reset Init nough o Wait cl= Enough 1 isp

Answer 1

Answer 1)

This the moore state machine as the output 'cl' and 'd' are dependent on the present state

VHDL CODE FOR GIVEN STATE MACHINE

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity State_Machine_Moore is
port (
Clk : in std_logic;
Reset : in std_logic;
Enough : in std_logic;
d, cl : out std_logic
);
end State_Machine_Moore;

architecture arch of State_Machine_Moore is
type state_type is (Init, Wait1, Disp);
signal presentState, nextState : state_type;
begin

Process1: process(Clk) -- Current State Logic
begin
if (Clk'event and Clk = '1') then -- positive edge triggered
if (Reset = '1') then -- synchronous active high reset
presentState <= Init;
else
presentState <= nextState;
end if;
end if;
end process Process1;


Process2: process (presentState) -- Next State
begin
case (presentState) is
when Init => cl <= '1'; d <= '0';
nextState <= Wait1;

when Wait1 => cl <= '0'; d <= '0';
if (Enough = '1') then
nextState <= Disp;
else
nextState <= Wait1;
end if;

when Disp => cl <= '0'; d <= '1';
nextState <= Init;

when others => nextState <= Init; cl <= '0'; d <= '0';
end case;
end process Process2 ;

end arch;