Question

thank you in advance

Sample Problem: MIPS is a 32-bit ISA. The I instructions in MIPS have the following format: [opcode (6bits)ー!RS (5 bits) (l6 bits) |1mm (16bits) Rt(5 bits) (1) Assume that we want to implement a single-cycle datapath for I MIPS instructions, write down the "in" ports part of the VHDL entity declaration for the single-cycle datapath controller. (Hint: what information does the single-cycle controller use?) entity singlecyclecontroller is port (???: in STD LOGIC); end foo; (2) Now assume that we want to implement a multi-cycle datapath, Write down the "in" ports part of the VHDL entity declaration for the multi-cycle datapath controller. (Hint: what additional information/signals does the multi-cycle controller need?) (3) Now assume that we want to implement a pipelined datapath with no data forwarding, Write down the "in" ports part of the VHDL entity declaration for the pipelined datapath controller. (Hint: what additional information/signals does the pipelined controller need?)

Answer 1

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