Question

B2 Consider a diode formed by making a p-n junction structure in a silicon sample as shown in Fig. B2. nt laver p-type Si Fig. B2 (a). If the dopant concentrations of the n layer and the p-type silicon are 6x101" cm and 8x10 cm respectively, calculate the built-in potential of the p-n junction at room temperature (300 K) 15 (3 marks) (b). Due to overheating of the silicon sample, the diode has an operation temperature of 200 °C and the intrinsic carrier concentration becomes 5.8x103 cm3 Calculate the built-in potential of the p-n junction in such a working condition. (3 marks) (c). Draw the energy band-diagram of the p-n junction in the open-circuited condition at room tempcraturc. All energy levels (such as Ec, Ev, E EFp and the energy difference related to the built in potential) must be clearly shown and labeled. (6 marks) (d, Descihe wath brief in plantios the seven key procesing f the (8 marks)

Answer 1

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d. Seven key processing steps to fabricate p-n junction are-

A. Silicon wafer cleaning (RCA process)

In the IC processing wafers it is necessary to maintain the purity and perfection of material. Silicon wafer is cleaned by standard RCA process. It useful to remove oil/grease, organic/ionic contamination, heavy metal ion and native oxide from the surface of wafer. Oil/grease/dust is removed by boiling wafer in trichloroethylene (TCE), acetone and methanol.

B. Oxidation

Process by which a layer of silicon dioxide (SiO2) is grown on a silicon substrate is known as oxidation. This process is carried out in a furnace in high temperature. In this process dry wet dry oxidation is performed. When silicon wafers are heated in a pure oxidizing gas ambient such as dry oxygen it known is as Dry Oxidation. Oxide layers are very uniform but Dry oxide grows very slowly i.e oxidation rate is very low When silicon wafers are heated in an ambience of wet oxidizing gas such as oxygen bubbled through hot D.I Water (carrying steam vapors) it is known as wet oxidation.

C. Photolithography

In I.C Technology, photolithography is used to transfer patterns made on a mask to a semiconductor wafer. Therefore, to fabricate a device or an I.C, the oxide layer needed to be removed from the Selective regions on silicon wafer, where diffusion is desired. First silicon wafer is coated with photo resist and exposed in ultra violet light. By the application of photo resist oxide layer is etched . Photo resist is an organic polymer, sensitive to UV light. It is temporarily coated on wafer surface to transfer design image on it through exposure in UV light.

D. Oxide etching

To remove SiO2 from regions exposed through photolithography is called oxide etching. After post bake, the wafer is dipped in Buffer HF solution for a particular time (determined by oxide thickness and etch rate) followed by thorough rinsing in D.I Water. It is called wet etching. To remove photo resist water cleaned wafer is boiled in acetone 2 min. to completely remove the photo resist from the wafer surface. If Wafer is subjected to Chemical Vapor Etching i.e subjected to a reacting gas mixture in a CVD reactor. It is called dry etching.

E. Diffusion

As the given wafer is N type so we need to diffuse P type impurity into the wafer to create P-N junction and we take Boron (P type) impurity for diffusion. Boron activation, pre deposition of boron and oxidation is going on. During boron activation a layer of B2O3 is formed on BN wafer. After that silicon wafer is placed with BN wafer and boron will diffuse in to silicon wafer.

F. Metallization

Metallization is the final step in the wafer processing sequence. Metallization is the process by which the components of IC’s are interconnected by aluminium conductor. This process produces a thin-film metal layer that will serve as the required conductor pattern for the interconnection of the various components on the chip. Another use of metallization is to produce metalized areas called bonding pads around the periphery of the chip to produce metalized areas for the bonding of wire leads from the package to the chip

G.Annealing

First step in IC fabrication is to introduce dopant atom. Implantation damages the target and displaces atoms from its site. The electrical behavior after implantation is dominated by deep level electron and hole traps, which capture carriers and make the resistivity high. Annealing is the process which is used to repair the lattice damage by putting atoms on substitutional sites where they will be electrically active