Question

The ARM9 microprocessor has a 5 stage pipeline and reads registers at the end of
stage 2 (decode) but writes values to registers in stage 5 (write-back).
6
i) How does this lead to a ‘read-after-write’ hazard?
ii) How is this problem eliminated using ‘data forwarding’?
iii) If the problem cannot be eliminated then an ‘interlock’ results; what is an
‘interlock’?

Answer 1

i). instruction I before instruction J in the program

instruction J tries to read operand before inst I writes it

I: add r1,r2,r3

J: sub r4,r1,r3

caused by dependence results from an actual need for comunication

ii). data frowarding is based on the fact that the data selected is not really used but in the next stage.

frowarding works as follows:

ALU results from EX\MEM buffer is always fed back to the ALU input keys. If the forwarding hardware detects that its source operand has a new value, the logic selects the newer result rather than the value read from the register file.

iii). Interlock is a hardware mechanism to enforce correctness. In "read after write" scenario stalling is necesary for proper execution which is done by pipeline interlock which stalls the pipeline until the hazard is cleared.