Question

2. To demonstrate a Mealy state machine, let's design a simple arbiter between two requesting entities. We're going to have two request inputs: reqA and reqB. And two outputs: grantA and grantB. Any combination of requests can be asserted at any time: one of them, both of them, or neither. But at most only one grant can be asserted in any given cycle; if neither request is asserted then neither grant should be asserted. We'll need a state machine to keep track of whose turn it is iin case both requests are asserted at the same time. I.e., in any cycle where both requests are asserted, the grant should go to whichever entity did not get the last grant. (a) Draw a state diagram for this behavior. (b) Create a state table, showing next states as a function of current state and inputs. [To keep things from getting too cluttered, we'll do the outputs as a separate table.] (c) Create a table showing how the outputs are a function of current state and inputs. (d) Write out the logic equations for the next state inputs to the flops, and for the output control signals 3. Now let's look at the Verilog implementation of the arbiter state machine. [Normally we would include an always block for the state update but we're not going to bother with that here.] (a) Define the module interface and the state variables you will use Also use a parameter statement so that vou can use labels for your states. Remember to define the output signals as type reg since you will be assigning to them inside the case statement, which is inside of an alwavs block. (b) Now write an always block that includes a case statement for determining both the next state transitions and the output value. Be careful to use begin/end statements where necessarv 4. Draw a circuit, using a 5-bit decoder, that implements the function f(A.B.C.DE)-6.17.19) וב)

Answer 1

the nuhs DE Rc Doo 0 0 SA