Question

The following register transfers are to be executed in, with minimum clock cycles:
S1' * S0' : R3 <- R0, R1 <- R2

S1 * S0': R2 <- R0, R1 <- R3

S1' * S0 : R3 <- R1, R0 <- R2

S1 * S0 : R2 <- R1, R0 <- R3

(a)What is the minimum number of buses required? Construct the register transfer operations so that the transfers can occur in one clock indicate the individual load line for each of the registers.

(b)Draw a block diagram connecting registers and multiplexers to implement the transfers

Answer 1

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