

Question 2 ARM Assembly Language (25 marks) An ARM instruction set summary is provided at the...
Section B - ARM Assembly Language (25 marks) An ARM instruction set summary is provided at the end of this paper 1. (5 marks) Consider the following assembly instruction STMFD r13!, (r5-6} Before executing this instruction, registers hold the following values: Register Value Register r9 Value r4 0x00400040 0x00000000 r5 r10 0x11223344 0x00800080 r6 0x55667788 r11 0x10001000 r7 0x99aabbcc r12 0x20002000 r8 exddeeff00 r13 ex40004000 What memory locations are affected after executing the above instruction? In a table, with a...
Write an equivalent C function and explain what it computes.
3. (10 marks) The following is the assembly language translation of a C function mystery: r3, [r0, #0] r3, #0 L3 ldrb cmp beq r3, #0 mov L4: r3, r3, #1 r2, [ro, r3] r2, #0 L4 add ldrb cmp bne .L3: ro, r3 lr mov bx Annotate each line of the function with commentss to explain what each line does. Write an equivalent C function and explain what it...
13) (4 pts) Squaring a number is useful in many other algorithms. This assembly routine calculates the square of an unsigned integer. How long does this take in clock cycles (worst case). Assume ARM 32 bit instruction set and the integer is in R0 before we begin. AREA L.textl, CODE, READONLY PROC EXPORT square square MOV R1,RO; CMP R1, #0 ANDS R3,RO,R1 BNE skip ADD RO,R1, LSL R3; MOV R2,R2, LSL #1 CMP R2, #0 BNE loop BX LR loop...
Exercise 2 (4 pts) Here is a logical instruction that is not included in the ARM instruction set. ANDN rl, r2, r3 @bit-wise AND of r2 and Ir3 (r2 and not r3) (2 pts) Provide a minimal set of ARM instructions that may be used in place of ANDN. 1ldr r2,0x0OFFASA5 2 ldr r3,OxFFFF003C 4 (2 pts) The above snippet starts with loading registers r2 and r3 with some values using instruction LDR. Why don't we use the instruction MOV?
This code needs to be written in Assembly language using Keil
uvision 5. Please use Keil Assembler. Or ARM assembly.
Thanks.
int main(void) { // initializing int R0 = 5; int R1 = 10; // for loop addition with CMP while(RO <=| 10) R$++; // for loop subtraction without CMP#10 while(R1 > 0) R1--; // if else statement if (RO > 0) R0 = 10; R1 = 10; else | R0 = 20; R1 = 30; // must using branching...
Assembly lang multiple choice Suppose we have the following pseudo-instruction in our program: push {r0, r2, r4} ..... Which of the following instructions would be the appropriate instruction to use when cleaning up the stack space used by the three register values that were pushed onto the stack? Group of answer choices sub sp, #12 add sp, #12 add lr, #12 2) Suppose we are comparing registers R1 and R2 and we want to branch if equal to the label...
Write an ARM assembly language program to translate the following sequence of statements . Assume x and y are memory locations that store two unsigned integers. Use the following: x is in R1, y is in R2, and z in R3. Make sure that your program works for any value of x and y. if (x > 15) { x = 1; if (y > 15) { y = 2; } else { y =...
Trying to figure out how to write expression #2 in assembly language: 1. ;;X=A*C+B*D MUL R4,R0,R2 MUL R5,R1,R3 ADDS R4,R4,R5 ;;X is in R4 I believe this is correct but Im having trouble with #2 below: 2. Y=A^(B+C)+D I've been using the arm cortex m4 instruction set for reference.
1. The following instruction(s),--, is (are) ARM® Cortex®-M4 assembly instructions. a. ui32int uiLoop c. void_WFI(void); d. WFI 2. The ARM® Cortex-M4 assembly instructions contain. a. Label field b. Operation field and operands field c. Operation field, op erands field and comment field d. Both a and c Copyrighted material Homework 245 3. The pseudo instruction DCW 2 is to a. Reserve 2-byte space for a data item in the program b. Reserve 2 hal f-word space for a data item...
Could you please help me doing this?
Slide #14:
Slide #15
The question:
ARM Assembly Language label mnemonic operand1, operand2, operand3 comments R2+R1->R3 Loc ADD R3, R2 R1 Label is a symbolic reference to this instruction's address in memory. Mnemonic represents the operation to be performed .The number of operands varies, depending on each specific instruction. Some instructions have no operands at all. operand1 is typically the destination register, and operand2 and operand3 are source operands. operand2 is usually a...