ld r1, 8[X19] /* value of x[1] is stored in r1 register (as each
integer takes 8 Bytes, X[1] = *(X+8)) */
sub r0, X20, r1 /* r0 := a - x[1] */
st r0, [X19] /* store r0 value into place whose address is X19
i.e., x[0] */
add X22, r0, X21 /* c := x[0] + b */
lsl r2, c, 4 /* r2 := c >> 4 */
st r2, 8[X19] /* store r2 value into place whose address is X19+8
i.e., x[1] */
mul r4, X20, 4 /* r4 := a * 4 */
ld r5, r4[X19] /* value from the address X19+r4 = x[r4/8] = x[a/2]
is loaded into r5 */
sum r3, r5, X21 /* r3 := r5 + b */
st r3, 16[X19] /* store r3 value into place whose address is X19+16
i.e., x[2] */
sum r6, r1, r3 /* r6 := x[1] + x[2] */
mul r7, X22, 8 /* r7 := c * 8 */
st r6, r7[X19] /* r5 is stored into place whose address is X19+r7 =
x[r7/8] = x[c] */
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4. Convert the below C code snippet to LEGV8 assembly code. Base address of x is...
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convert C to LEGv8
(an example given below)
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B2. Convert the C code to MIPS assembly with only 2 efficient instructions: Register assignment: timer-v0 int timer = 0x0AC8 0001; B3. Write...
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IN MIPS AND MUST RUN IN QTSPIM
Translate the following C code to MIPS assembly code. Use a minimum number of instructions. Assume that the values of a, b, i and j are stored in registers Ss0, Ss1, St0 and Stl, respectively. Also assume that register Ss2 holds the base address of the array D. for (i=0; i<a; itt) for (i-0j<b:jt+)
its
brr[8]
(40%) Convert the following C-pseudo code into MIPS assembly code as a standalone program (including main and all the required directives). You can use any register. You must comply, however, with the convention of register usage. Before writing your code perform an explicit register allocation phase. Note that the C snippet is int arr[8]; int brr[4]-{1, 2, 3, 4, 5, 6, 7, 8) int i-8; while (i>-0) arrli]-brr[i-); (40%) Convert the following C-pseudo code into MIPS assembly code...