Question

Write the following program to be executed on the FPGA board. 1. Write a VHDL model for a code detector as shown in the Figure. The keypad is used to unlock a door. Pressing the start button followed by the sequence red-green-red-blue unlocks the door, no other sequence can open the door. Assume the clock is slowed down and each pressing of a button is detected once. For example when red is pressed it is only detected as pressed for one clock cycle. reset start Code Door Lock red Detector green blue Key Pad I Four lights are connected to a decoder. Design a controller that will blink the lights in the following order: 0, 2, 1, 3,0, 2,. the controller output is the binary code for the light number. For example for turning on light 0, s1= 0, s0 = 0. To turn on light 2, s1 1, s0 = 0. Start from a state diagram, draw the state table, minimize the logic, and draw final logic circuit at gate 1. level, s1 Controller 0 1 Decoder

Answer 1

CODE DETECTOR

--VHDL CODE

START So DOOR START +b S5 SI DOOR DOOR htb b tb S4 DOOR S2 DOOR h S3 DOOR MOORE STATE MACHINE

library ieee;
use ieee.std_logic_1164.all;

entity code_detector is
   port (   clock   : in std_logic;
       reset   : in std_logic;
       r   : in std_logic;
       g   : in std_logic;
       b   : in std_logic;
       door_lock   : out std_logic
   );
end code_detector;

architecture arch of code_detector is

type state is (S0, S1, S2, S3, S4, S5);

signal current_state, next_state : state;

begin

process (clock)

begin

   if rising_edge (clock) then

       current_state <= next_state;

   end if;

end process;

process (current_state, reset, r, g, b)

begin

   case (current_state) is

       when S0=>    if (reset = '1') then
                   next_state <= S1;
               elsif (r = '1' or g = '1' or b = '1') then
                   next_state <= S0;
               end if;
               door_lock <= '0';

       when S1=>    if (r = '1') then
                   next_state <= S2;
               elsif (reset = '1' or g = '1' or b = '1') then
                   next_state <= S0;
               end if;
               door_lock <= '0';

       when S2=>    if (g = '1') then
                   next_state <= S3;
               elsif (reset = '1' or r = '1' or b = '1') then
                   next_state <= S0;
               end if;
               door_lock <= '0';

       when S3=>    if (r = '1') then
                   next_state <= S4;
               elsif (reset = '1' or g = '1' or b = '1') then
                   next_state <= S0;
               end if;
               door_lock <= '0';

       when S4=>    if (b = '1') then
                   next_state <= S5;
               elsif (reset = '1' or r = '1' or g = '1') then
                   next_state <= S0;
               end if;
               door_lock <= '0';

       when S5=>    next_state <= S0;
               door_lock <= '1';

       when others=>     next_state <= S0;

   end case;

end process;

end arch;

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--Simulation on ModelSim

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M ModelSim- INTEL FPGA STARIER EDITION 10.5b File Edit View Compile Simulste Add Wave Tools Layout Bookmarks Window Help d M E Search: T A 100 pa国国国國的一 || XX Layout simulate it x byects Ansarpt : 194 ps Wave-Default Msns d detect wiet/code dete Icode detector fdloo L ctor/ 0 0 Ine_22 reset code detector freset 4 im:rde d Icode_detectorr sterderd ctor/b 7> run texto 4b rade deterter std logic 11 run code detector /door Jock ste code detector/current state kcode_detector/next_state s0 next state VSIM 58 run force -freeze dete Eorce-freeze ctor/reset 10 erce-freeze sim:/code_dete icbve) Name sini/code dete VSIM 63> zun ctor/ 0 0 ctor/g0 force -freeze dete ctor/a 01 force -freeze /code_dete VSIM 69> run Now 1700 ps 1400 ps 1600 ps Cursor 1 1194 ps 1194 ps VSIM Z0 run 4 SIM 70 H code detector.vhd Wave sim:/code detector 0ps to 1785 ps Now: 1,700 ps Delta: : 7:43 PM M Type here to search 6/19/201g

BLINKING CONTROLLER

STATE DIAGRAM & STATE TABLE is shown below:

Here LO, L1, L2 and L3 represents four states and S1, S0 are the outputs of the Moore State Machine

LO SISO LI L3 OSTS OSTS L2 SI SO

We will implement FSM using D Flip Flop and derive expressions for states and outputs using Karnaugh Maps as shown below

CONTROLLER CIRCUIT

QIt=2IQ0+Q1Q0 RO+ QI+= Q1QO P/PO \QO 1 1 S1= QO

x1) Q1 Deno x1 Q0 'DenO CLOCK x1 S1 S0 X1