Study Section 13.4, General Models for Sequential Circuits. (a) A Mealy sequential circ...

Study Section 13.4, General Models for Sequential Circuits.

(a) A Mealy sequential circuit has the form shown. The combinational circuit realizes the following equations:

Initially, X₁ = X₂ = 1 and Q₁ = Q₂ = 0 as shown.

(1) Before the falling clock edge, show the values of the four combinational circuit outputs on the preceding diagram and on the following timing chart.

(2) Show the signal values on the circuit and timing chart immediately after the falling edge.

(3) Show any further changes in signal values which will occur after the new values of Q₁ and Q₂ have propagated through the circuit.

(4) Next change X₁ to 0 and repeat steps (1), (2), and (3). Show the values for each step on the circuit and on the timing chart.

(5) Next change the inputs to X₁ = 1 and X₂ = 0 and repeat steps (1), (2), and (3).

(6) Change X₂ to 1 and repeat.

(b) Draw a block diagram for a general model of a Mealy circuit, using J-K flip- flops as memory elements. If the circuit has n output variables and k flip-flops, how many outputs will the combinational sub circuit have?

(c) If the circuit of Figure 13-5 were not synchronized using a clock, but instead, the flip-flops were updated continuously, and if the XOR gate had a longer delay than the OR gate, what problem could appear?

(d) The minimum clock period for a Moore circuit is determined the same way as for a Mealy circuit. Should t_c be determined by the combinational sub circuit for the flip-flop inputs or for the outputs? (See Figure 13-19.)

(e) We can think of the binary counter of Figure 12-15 as a Moore circuit if we say the outputs Z₁, Z₂, and Z₃ are Z₁ = A, Z₂ = B, and Z₃ = C. (The combinational sub circuit for outputs has no gates, but that is okay.) If the XOR gates have a propagation delay of 4 ns and the AND gate has a propagation delay of 2 ns, what is the longest total propagation delay through the combinational sub circuit for flip-flops (i.e., the XOR gates and the AND gate) to the D inputs of the flip-flops? If the flip-flops have t_su = 3 ns and t_p = 3 ns, what is the minimum clock period for the binary counter?

(f ) In Equations (13-6) and (13-7), what do the symbols δ and λ mean?

Equation (13-7) is for a Mealy circuit. What is the corresponding equation for a Moore circuit?

(g) For Table 13-5,