a) Design a system using only FETs, capacitors. and other basic electric circuit elements (no higher-level gates or registers) to have two sample-and-hold circuits connected to a common line via three-state buffers, with the following properties: 1) each sample-and-hold element has a word line (WL) that connects it to the common line when the word line is high and disconnects it when the word line is low; 2) when a sample-and-hold element is connected to the common line, if an external output is also connected to the line, it will write the value of the external output to the sample-and-hold element; and 3) when a sample-and-hold element is connected to the common line, if no external output is also connected to the line, an external detector can read the value of the sample and-hold element.
b) For a better circuit, add logic to prevent both sample-and-hold elements from connecting to the line if for some reason both word lines go high at the same time.
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