Consider the basic diff-amp with active load and current biasing in Figure 13.14. Using the parameters and results of Example 13.8, determine the maximum range of common-mode input voltage under the conditions that the minimum source-to-drain voltage for a PMOS is limited to uso(min) = 1)5D (sat) + 0.2 V and the minimum drain-to-source voltage for an NMOS is limited to υDs(min) = υDs (sat) + 0.2 V.
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