Find the syntax errors in the following declarations (note that names for primitive gates are optional):
| module | Exmpl-3(A, B, C, D, F) | // Line 1 |
| inputs | A, B, C, Output D, F, | // Line 2 |
| output | B | // Line 3 |
| and | g1(A, B, D); | // Line 4 |
| not | (D, A, C), | // Line 5 |
| OR | (F, B; C); | // Line 6 |
| endmodule; |
| // Line 7 |
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