Study Section 20.2, VHDL Code for a Binary Multiplier. (a) In Figure 20-2: Why are M...

Study Section 20.2, VHDL Code for a Binary Multiplier.

(a) In Figure 20-2: Why are Mplier, Mcand, and ACC declared as type std_logic_vector instead of bit_vector?

After what state change does Done change from '1' to '0'?

When adding Mcand to ACC(7 downto 4), why is '0' concatenated to ACC(7 downto 4)? (line 29)

What does the notation when 2|4|6|8 mean? (line 34)

(b) In Figure 20-3:

Why is the initial value of ACC “UUUUUUUUU”?

When should the product be read?

(c) If the signal X, of type std_logic_vector(8 downto 0), is “111001101” initially, what is X after the execution of the following for loop? How long does it take?

(d) In Figure 20-5, on lines 29 and 30, when i = 2 and Done = ‘1’, what are the values of Mcand and Mplier? What is the value of Product if the multiplier is working properly?

(e) In Figure 20-7:

Which statement represents the adder?

Why are Load, Ad, Sh, and Done set to '0' (line 22) before the case statement?

Write a single VHDL statement that will clear ACC(8 downto 4) and load ACC(3 downto 0) with Mplier, so that lines 39 and 40 can be replaced with a single line.

Why is addout loaded into ACC in the second process instead of the first process?

In Figure 20-2 we set Done <= '1' in a concurrent statement (line 42), and not after when 9 => on line 37 in the process. Why?

(f ) In Figure 20-9:

When does the statement in line 22 execute?

If Sh = '1', which statements execute following a rising clock edge?

If the clock rises at t = 10 ns, at what time are A, B, Count, and State updated? Explain why A and B are shifted as a unit even though the statements for updating A and B execute in sequence (line 51).

(g) In Figure 20-10 at time = 60 ns, explain the contents of the registers after the rising clock edge. (Hint: Refer to Figure 18-9(c) to determine what happens in state 2 when K = '0'. Convert hexadecimal to binary and shift the binary before converting back to hexadecimal.) Repeat for time = 140 ns, noting that M = '1' before the rising clock edge.

(h) Read Appendix C, Tips for Writing Synthesizable VHDL Code.

(i) Work Problems 20.1, 20.2, 20.3, and 20.4.