Study Section 16.5, Sequential Circuit Design Using CPLDs, and Section 16.6, Sequential...

Study Section 16.5, Sequential Circuit Design Using CPLDs, and Section 16.6, Sequential Circuit Design Using FPGAs.

(a) How many macrocells of a CoolRunner-II are needed to implement a Moore machine with six states, one input, and two outputs? With two inputs?

(b) How many LUT’s of a Virtex/Spartan II are needed to implement each of these Moore machines? How many CLB’s?

(c) Rewrite the equations for of Equations 12-1 to fit into one LUT each, as we did for in Equation (16-2), using CE = Ld + Sh.