Write the VHDL code for RS Flip flop.

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Question

Write the VHDL code for RS Flip flop.

engineering Electrical-Engineering

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Answer 1

Answer #1

Truth table for RS Flip Flop

Q R S Q(N+1)

0 0 0 0(Memory state same as Q)

0 0 1 1

0 1 0 0

0 1 1 UNKNOWN

1 0 0 1(Memory state same as Q)

1 0 1 0

1 1 0 1

1 1 1 UNKNOWN

CODE BELOW

library ieee;

use ieee. std_logic_1164.all;

entity SR-FF is

PORT( S,R,CLOCK: in std_logic ; Q , QBAR: out std_logic);

end SR-FF;

Architecture behavioral of SR-FF is

begin

PROCESS(CLOCK)

variable x: std_logic;

begin

if(CLOCK='1' and CLOCK'EVENT) then

if(S='0' and R='0')then

x:=x;

elsif(S='1' and R='1')then

x:='Z';

elsif(S='0' and R='1')then

x:='0';

else

x:='1';

end if;

Q<=x;

QBAR<=not x;

end PROCESS;

end behavioral

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Answer 2

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Write the VHDL code for RS Flip flop.

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Write the VHDL code for RS Flip flop.

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