Question

Use your answer from above to modify the VHDL code provided for the D Flip-Flop in Section

4.3 to implement the new synchronous reset and load functions. Simulate functionality.

RST LOAD CLK Synchronous reset Load Data Retain Value Retain Value Retain Value Retain Value

Answer 1

VHDL code module syn sutput eg[ 6:01o, output xeg o1 input 6:01 DFLIP, input loadsleskxeset.n) always (pesedge clock) if.(!reset n)(Q1,아<=9, bO; //synchronous reset else if (load) (Q1,아<=DFLIP; //synchronous load else (Q1, 와 <-o+1, b1; //synchronous increment endmodule

program code library ieee use ieee.std logic 1164.al1: use ieee.std lo unsigned all; entity syn 1S pezt ( clockk: in std logici ri in std legisi DFLIP: in std logic eset n loadi in std logici 2.w, out std logic vector ( 6 downtw 0); i out stdlegis); end syni

architecture retal of syn is signal count : std legi vestax (7 downto 0 begin 01 <= count(7); Q<= count(6 downto 0); precess (clock) if (clock'event and clock= 'l') then if (reset n- '0') then count(others'0)//synchronous reset elsif (load = countに'0' & DFLIP; //synchronous load '1' then else 1;--synchronous increment end if; countにcount end ifi end process; end retal;