Question

The characteristic table and schematic symbol of a positive edge-triggered D flip-flop with an active high asynchronous reset and an active high synchronous clock enable is given below. Study the table to understand the functional specification of the D flip-flop. Then, perform the following procedure. RST CLK EN D Q(t+1) Comments 1 X XX0 Asynchronous reset. D RST Q CLK EN Q | X | | X|X| | 0 |X| | 0 | Low clock level. No state change. 0 0 1X X ↓ 0(t) Q(t) High clock level. No state change. 0 | Negative/falling clock edge. No | state change. Q(t) Positive/rising clock edge. D flip-flop is | synchronously DISABLED. Next state is the same as the present state. ↑ Q(t) 0 1 0 0 Positivelrising clock edge. D flip-flop is synchronously ENABLED. Next 0 1 1 1 1 state is same as the D input.

Use the Quartus Prime Text Editor to implement a behavioral model of the D flip-flop described above in a file named d_flops.sv. Specify the D flip-flop’s module according to the interface specification given in the table below.

Port	Mode	Data Type	Size	Description
RST	in	logic	1-bit	Active high asynchronous reset
CLK	in	logic	1-bit	Synchronizing clock signal
EN	in	logic	1-bit	Synchronous clock enable
D	in	logic	1-bit	Synchronous data input
Q	out	logic	1-bit	Current/present state
Qbar	out	logic	1-bit	Inverted current/present state

Within the module implementation, model the D flip-flop using the following modeling specifications:

• Declare an intermediate signal named Qtemp of type logic. Signal Qtemprepresents the current state of the D flip-flop.

• Utilize a concurrent sensitivity-list always_ff @ ( ) statement to represent the behavior of the D flip flop. Which signal(s) should be included in the sensitivity list?(Don’t forget to enclose this in a begin – end block if needed)

• Within the sensitivity list, detect the rising edge of port signals CLK and RST using the keyword posedge. See the example below:

  always_ff @(posedge name_signal)

• Within the implementation portion of the always @ statement, use nestedsequential if statements to model the behavior of the D flip-flop. What signal(s), if any, have priority? (Don’t forget to enclose this in a begin – end block if needed)

• Properly assign port signals Q and Qbar.

Answer 1

//D Flip Flop in SV
module d_flop(
input logic RST,CLK,EN,D, //Input port Declaration
output logic Q,Qbar //Output port Declaration
);

logic Qtemp; //Internal Variable

//Sequential BLOCK using nested if
always_ff @(posedge CLK or posedge RST) begin
if(RST) //Set = 1 or posedge of RST
Qtemp <= 1'b0;
else if(EN) //EN = 1
   Qtemp <= D;
else //EN = 0, HOLD previous value
Qtemp <= Qtemp;
end
  
//Assigning Output Ports
assign Q = Qtemp;
assign Qbar = ~Qtemp;

endmodule

//Testbench in SV
module test;
logic RST,CLK,EN,D,Q,Qbar;

//Instantiation of D Flip Flop
d_flop DFF(RST,CLK,EN,D,Q,Qbar);

//Driving Clock
always begin
#5 CLK = 1'b0;
#5 CLK = ~CLK;
end
  
//Driving Stimulus
initial begin
RST = 1'b1;
@(posedge CLK) RST = 1'b0;
EN = 0; D = 0;
@(posedge CLK) EN = 0; D = 1;
@(posedge CLK) EN = 1; D = 1;
@(posedge CLK) EN = 1; D = 0;
@(posedge CLK) EN = 1; D = 1;
@(posedge CLK) EN = 0; D = 0;
@(posedge CLK) EN = 1; D = 1;
@(posedge CLK) $finish;s
end
endmodule

//Simulation Waveform

//Quartus Synthesis

ModelSiM PE StUdent Edition 10.Aa File Edit View Compile Simulate Add Wave Tools Layout Bookmarks Window Help 乡沩 兴置 ILI ■ 豳//..Г. l Wave -Default 1h0 thi 1ho Oursor 1 62 ns Trarscrpt Objects Now: 80ns Delta: /test/ #NTTAL # 40 0 ns to 84ns

Ouartus Pnme uite Edition Flle Edit View Project Asslenments Processing Tools Window Help Compilation Repart-d_flap Catalog Table of Contents Flow Summary Flow Settings Flow Non-Default Glabal Settir Quartus Prime Version Flow Elapsed Time Flow OS Summary Installed 1P Project Directory àCyclone IV E:AUTOo d rlop Flow Status Successtul Mon Mar 25 0503:29 2019 8.1.0 Build 625 09/12/2018 SJ Lite Edition d_flap d flop Cyclone IE No Selection Available Library Top level Entity Name Family latal lagic elerments To al registers Basic Funcions DSP Interface Pratorals Mcmory Interfaces and Controllers Processors and Peripherals EFlow Log > Analysis & Synthesis Flow Messages Flow Suppressed Messages Total pins latal virtual pins Total memory bits Embedded Multiplier 9-bit elements Iatal PLL Uriversity Prograrn ● 5c rch for Partner in 0 Tasks Compilation Task Compile Design Analysis & Synthesis Fitter (Place & Routel Assembler (Generate program Timing Analysls EDA Netlist Writer Filter Find.. ee Find Next TVDe ID essage 0 20030 Parallecoilation is enabled and will use 4 of the 4 processors detected 12021 ound 2 des ign units, inc luding 2 entities, in source file /users/vinay/desktop/d flops/d flops. sv 12127 Elaborating entity "d flop" for the top level hierarchy 0 286030 Timing-Driven Synthesis is running 16010 Generating hard_block partition "hard block:auto_generated inst" 0 21057 Implemented / device resources after synthesis - the final resource count might be different Quartus Prime Analysis &Synthesis was successful. errors, 1 warning System Processing (11 100% 00:00:30

File Edit View Tools Window Help Page 1 of 1 ..İNetlistNavigator d flop:1 + ad-flap Qtemp Qbar-not CLK CLK ENA SCLR Qbar 1'hO CLRN RST 100% 00:00:02