Question

1. The D Flip-Flop ) Look for the datasheet of the 7474 D flip-flop and wire it on the breadboard making sure to supply 5V to both Preset and Clear. Utilize the function generator to provide a Clock signal of 1 Hz: i) Press AMPL and set value to 5 Vpp ii) Press FREQ and set value to 1 Hz ili) Press OFFSET and set value to 2.5 V This Clock signal will be the same for all circuits in this experiment. Monitor the outputs by using resistors and LEDs. The provided D flip-flop is a positive-edge triggered device with asynchronous Preset and Clear. How does the output Q behave in response to input D? b) With the information gathered from step b), fill out the characteristic table corresponding to aD flip-flop c) ELEE/CMPE 2130 d) Change input Preset to LOW and record the outcome. Q- Change input Preset back to HIGH. Change input Clear to LOW and record the outcome. Q = e) Change input Clear back to HIGH. 2. The T Flip-Flop a) Build the circuit below equivalent to a T flip-flop. Remember to provide 5V to both Preset and Clear for the D flip-flop. Use a 1 Hz Clock signal. Use resistors and LEDs to monitor the outputs. D a b) How does output Q behave in response to input T? c) With the information gathered from step b), fill out the characteristic table corresponding to a T flip-flop. 0 d) With the information gathered from step c), complete the following timing diagram. Olock Preset 3. The JK Flip-Flop a) Look for the datasheet of the 7476 JK flip-flop and wire it on the breadboard making sure to supply 5V to both Preset and Clear. Use a 1 Hz Clock signal. Use resistors and LEDs to monitor the outputs. The provided JK flip-flop is a negative-edge-triggered device with asynchronous Preset and Clear b) How does output Q behave in response to all four different combinations of inputs Jand K? c) With the information gathered from step b), fill out the characteristic table corresponding to a JK flip-flop. 0 d) e) Change input Clear to LOW and record the outcome. Q f With the information gathered from steps a) through e) above, complete the following timing Change input Preset to Low and record the outcome. Q = Change input Preset back to HIGH. Change input Clear back to HIGH. diagram. Clock Preset Cear 4. The Three-bit Ripple Counter a) Build and demonstrate to the lab instructor the circuit shown below using resistors in series with LEDs to monitor outputs A, B and C. When the input signal Set is LOW every output is also LOW, when the input signal Set is HIGH the circuit becomes operational. vce เงิ NFFF Clock CLPN 10 CLRN CLRN Set b) Observe the behavior of the circuit above and complete the following timing diagram

Answer 1

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