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Part I Consider the circuit in Figure 1. It is a 4-bit synchronous counter (text Section 5.9.2) that uses four T-type flip- flops (text Section 5.5). The counter increments its value on each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear b signal low - it is an active-low asynchronous clear. You are to implement an 8-bit counter of this type Enable T Q T Q Clock Q Clear b Figure 1: A 4-bit counter. Perform the following steps: 1. Draw the schematic for an 8-bit counter using the same structure as shown in Figure 1 2. Write a Verilog module for a Ttype flip flop (text Section 5.5). 3. Write the Verilog module corresponding to your schematic. Your code should use your T-type flip-flop module that is instantiated eight times. 4. Simulate your circuit to verify its correctness.

please give the verilog code and explain in the form of comments.

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