Question

10.21 Write a behavioral Verilog module vrDnegEc for a negative-edge-triggered D flip-flop with enable and asynchronous active-low clear. Also write a test bench that instantiates your flip-flop and exercises its operation for a comprehensive input sequence.

Answer 1

code:

module VrDnegEC(rst,en,clk,d,q);
input rst,clk,d,en;
output q;
reg q;
always @(negedge clk)
begin
if(en==1)
begin
if(rst==0)
q<=0;
else
q<=d;
end
else
q<=0;
end
endmodule
module test;
reg rst,clk,d,en;
wire q;
VrDnegEC uut(rst,en,clk,d,q);
initial
begin
rst=0;
#10 rst=1;d=1;en=1;
#10 rst=1;d=0;en=1;
#10 rst=1;d=0;en=1;
#10 rst=1;d=1;en=1;
#10 rst=1;d=1;en=1;
#10 rst=1;d=0;en=1;
#10 rst=1;d=0;en=1;
#10 rst=1;d=1;en=1;
end
initial
begin
clk=1;
forever #10 clk=~clk;
#100 $stop;
end
endmodule

simulation:

Name alue 0 ns 200 ns 400 ns 600 ns 800 ns rst 11 ARARHI TARHALInnnILHHRR