Model the following using Structural Verilog and write a Test Bench. a. Half adder b. Full...

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Model the following using Structural Verilog and write a Test Bench. a. Half adder b. Full adder c 4 1 Multiplexer d. 2-to-4-Line Decoder 2. Model the following using Behavioral Verilog and write a Test Bench. a. Half adder b. 4-bit Up counter c. Positive edge triggered D Flip Flop d. Positive edge triggered JK Flip Flop

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Model the following using Structural Verilog and write a Test Bench. a. Half adder b. Full...

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Model the following using Structural Verilog and write a Test Bench. a. Half adder b. Full...