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Problem 1. a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset. b) Write...

Problem 1.

a) Write a behavioral model of J-K flip-flop with active-low asynchronous reset.

b) Write a proper test-bench and stimulus, thoroughly test your J-K-FlipFlop. Also, show your waveform and describe why your JK-FF does what is is designed to do.

Problem 2.

a) Write a Verilog module that will assert its output if a 4-bit input binary word is even.

b) Show the waveform for two input patterns “1100” and “0101”

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Answer #1

answer1

a.)

an async. reset mean the reset/ clear can occur even when there is no posedge of clock at the time

an active low keword mean that the rest value for activation will be 0 instead of 1

module jkffpos(j,k,q,clk,clear);
input j,k,clk,clear;// inputs
output reg q=0;
always@(posedge clk,negedge clear)// active low async. reset and clock sensitivity
begin
if(!clear)// active low check
q<=0;
else
begin
case({j,k})// output selction based on inputs j-k
0: q<=q;
1: q<=1;
2: q<=0;
3: q<=~q;
endcase
end
end
endmodule

b.) testbench:

module test();
reg j,k,clk,clear;
wire a;
jkffpos j1(j,k,a,clk,clear);
  
initial
begin// sending inputs to the design
clk=0;clear=1;j=0;k=0;
#2 clear=0;
#4 clear=1;j=0;k=0;
#1 j=1;k=1;
#8 j=0;
#4 j=1;k=0;
#4 j=0;
#10 $finish;
end
initial// wave genration from dump files
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial// clock generation
forever
#2 clk=~clk;
endmodule

answer 2.)

the parity can be check if we xor all bit of the input to itself. if the result is 0 then even if the result is 1 then odd parity is detected.

here even is 1 if the input has even parity.

module even_parity_checker(in,even);
input [3:0] in;
output even;
  
wire w1,w2,w3;// internal wires
  
xor x1(w1,in[0],in[1]);// xor gate
xor x2(w2,in[2],in[3]);
xor x3(w3,w1,w2);
not n1(even,w3);// used to give an active high output for even
endmodule

b.)

module test();
reg [3:0] in;
wire even;
  
even_parity_checker c1(.*);// automatic connection of testbench and design if names of the ports are same
  
initial// giving input values
begin
in=4'b1100;

  1. #2 in=4'b0101;

#2 $finish;
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

waveform:

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