Question

Lab Description Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and use your ALU from Lab 3 to create an accumulator-based processor. This will act ike a simple processor; the ALU will execute si operations and each result will be stored in the register. In an accumulator, the value of the register will be updated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register You will create and implement this accumulator-based processor in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board's clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: n Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF) a) In your design, use inputs "D" (data), "CLK" (the clock), "RST (an asynchronous reset setting the output to 0), "SET (a synchronous set or preset signal setting the output to I), "CE" (clock enable), and output "Q b) Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i The output "Q" sampling a '0 from the input "D" )The output "Q" sampling a '1from the input "D The correct operation of the asynchronous reset The correct operation of the synchronous preset )The correct operation of the clock enable e pt] Place your flip-flop's VHDL design module code here (copy- paste as text, not an image): Place a screenshot of your simulation here (enlarge your wavefornm and do not crop the image (it should show the whole screen) or you will lose points): e[1 pt] According to your simulation, at what simulation time(s) does the output "Q" sample a ‘0, from the input "D"? 01 1 pt1 According to your simulation, at what simulation time(s) does

Answer 1

VHDL behaviouwal model Jom RET D-frp flop: est std-1ogc Dout out Std- logc);, end Dff; be Process et,Clock,Dn) be (eset-,'then end ใ.pl end Psocess ; end Behovional: Test bench code . Lt End DPF- tb Component DFP PoRT CS

Dout out std-logic) end Compone nt Signal clocK . Std-logic : = 0 Sig Dout: Std-logic; constant clocK-Pes l: ime :onsi Begin clock clock Reset ) Resek , Bout ) ou) be clock仁1,1 end Phocess' Stim-Proc : Process wai+ for 50 ns') wo for 50 ns cS Process:

11 0.05KB/SM O 5:27 49% 4G Output: 50 ns 100 ns Name Value ns din edlk rst dout