Question

1. Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code
2. Simulate the circuit using ISim and analyze the resulting waveform.
3. Take full screenshots of all Verilog source codes and the resulting simulation waveform to be included in the lab report. Include explanation of the waveform and how you can conclude that the D flip flop implemented in step 9 is correct in the lab report.

Verilog Code for dff_fe_asyn_h is mentioned below:-

//DFF module with asynchronous active high reset with negative edge trigger with clock
module dff_fe_asyn_h (
input clock, // Clock Input
input reset, // Reset Input
input data_in, // Input Data
output reg data_out // Output Data
);

always @ (negedge clock or posedge reset) // triggers at the negative edge of the clock
begin
if (reset) // Asynchronous Active High reset
data_out <= 1'b0;
else
data_out <= data_in; // When reset is not present then it forward the input data to output
end

endmodule

Answer 1

Solution :-

Part 1) :- Verilog design code

module dff_fe_asyn_h (
input clock, // Clock Input
input reset, // Reset Input
input data_in, // Input Data
output reg data_out // Output Data
);

always @ (negedge clock or posedge reset) // triggers at the negative edge of the clock
begin
if (reset) // Asynchronous Active High reset
data_out <= 1'b0;
else
data_out <= data_in; // When reset is not present then it forward the input data to output
end

endmodule

Tesbench code

`timescale 1ns / 1ps

module test_bench;

// Inputs
reg clock;
reg reset;
reg data_in;

// Outputs
wire data_out;

// Instantiate the Unit Under Test (UUT)
dff_fe_asyn_h uut (
.clock(clock),
.reset(reset),
.data_in(data_in),
.data_out(data_out)
);

always
#5 clock = !clock;
  
initial begin
// Initialize Inputs
clock = 1'b1;
reset = 1'b1;
data_in = 1'b0;
#20;
reset = 1'b0;
#40;
data_in = 1'b1;
#40;
reset = 1'b1;
#20;
reset = 1'b0;
data_in = 1'b0;
#30;
$finish;
end
  
endmodule

Snapshot for the Isim tool:-

Waveform of the testbench:-