Question

1. Write a test bench to thoroughly test the Verilog module dff_fe_asyn_h. below is the module ddff_fe_asyn_h.code
2. Simulate the circuit using ISim and analyze the resulting waveform.

Verilog Code for dff_fe_asyn_h is mentioned below:-

//DFF module with asynchronous active high reset with negative edge trigger with clock
module dff_fe_asyn_h (
input clock, // Clock Input
input reset, // Reset Input
input data_in, // Input Data
output reg data_out // Output Data
);

always @ (negedge clock or posedge reset) // triggers at the negative edge of the clock
begin
if (reset) // Asynchronous Active High reset
data_out <= 1'b0;
else
data_out <= data_in; // When reset is not present then it forward the input data to output
end

endmodule

Answer 1

TEST BENCH:

module tb;
reg rclock,rreset,rdata_in;
wire wdata_out;

dff_fe_asyn_h m1(rclock,rreset,rdata_in,wdata_out);

always
#5 rclock=!rclock;

initial
begin
rclock=0;
@(negedge rclock)
rreset=1;
@(negedge rclock)
rreset=0;
$display(wdata_out);
rdata_in=1;
@(negedge rclock)
$display(wdata_out);
#100 $finish;
end

endmodule