Question

VERILOG CODE

Design a new Verilog module to define a 4-bit counter algorithmically using behavioral modeling. This time we no longer need T FlipFlop submodule. The 4-bit counter can be directly implemented using a 4-bit register variable and adding 1 to its value as follows:

input Clock, Clear, Enable;

output reg [3:0] Q;

always @ (posedge Clock or negedge Clear)

if (~Clear) Q <= 0;

else if (Enable)

Q <= Q + 1'b1;

Answer 1

the verilog module:

module counter(out_count,clk,reset);
input clk,reset;
output reg [3:0] out_count=0;
always@(posedge clk)
begin
if(!reset)
begin
out_count<=0;
end
else
begin
out_count<=out_count+1;
end
end
endmodule

testbench:

module test();
reg clk,reset;
wire [3:0] out_count;
counter c1(out_count,clk,reset);
initial
begin
clk=0;reset=0;
#2 reset=0;
#4 reset=1;
#40
#4 reset=0;
#4 reset=1;
$finish;
end
initial
forever
#2 clk=~clk;
initial
$monitor("out_count=%b",out_count);
endmodule

waveform: