Question

help me to finish the verilog code and test bench

Part 2: Sequence Counter

Design the sequence counter using Xilinx Vivado. Consider the required number of D flip-flops(4). A sample VERILOG source file is as shown:

module Seq_COUNT(

    ??? clock,

    ??? wire [?:?] D,

    ??? ??? [?:?] out

    );

    always @ (??? ???)

    ???

        // 3 bit Sequence Given is 0 2 4 6 1 3 5 7

        out[N-1] <= some expression;

           ⁞

        out[0] <= some expression;

    ???

   

endmodule

The requisite test bench file mirrors the test bench file used for the shift register with the following changes:

    always #15 ? = ? ?; //invert the clock_t input using this period

    always #10 ? = ? ?; //invert the D_t[0] input using this period

             ⁞

    always #? ? = ? ?; //invert the D_t[N-1] input using the period that is //double the previous period

Answer 1

module Seq_COUNT(
input clock,
input wire [2:0] D,
output reg [2:0] out
);

always @(posedge clock)
begin
     out[0] <= !(D[0] ^ D[1] ^ D[2]);
     out[1] <= !D[0];
     out[2] <= D[1];
end

endmodule

module testbench;
reg        clock_t;
reg [2:0] D_t;
wire [2:0] out_t;

always
   #15 clock_t = !clock_t;

always
   #10 D_t[0] = !D_t[0];

always
   #20 D_t[1] = !D_t[1];

always
   #40 D_t[2] = !D_t[2];

// DUT instantiation
Seq_COUNT DUT0 (.clock(clock_t), .D(D_t), .out(out_t));

always @(posedge clock_t)
    $display("D = %b, OUT = %b", D_t, out_t);

initial begin
clock_t = 1'b0;
D_t = 3'd0;
#300 $finish;
end
endmodule

/************ OUTPUT OF PROGRAM **********
D = 001, OUT = xxx
D = 100, OUT = 000
D = 111, OUT = 010
D = 010, OUT = 100
D = 101, OUT = 110
D = 000, OUT = 001
D = 011, OUT = 011
D = 110, OUT = 101
D = 001, OUT = 111
D = 100, OUT = 000
*****************************************/