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I need help writing the Verilog Design code for this test bench. I have to calculate...

I need help writing the Verilog Design code for this test bench. I have to calculate the dot product of two 8-bit vectors a and b. I have listed the test bench below:

// Code your testbench here

module test_VVM;
wire [3:0] value;
wire done;
reg clk, rst;
reg [7:0] a, b;

initial
begin
a = 8'b11011101;
b = 8'b11010111;
   clk = 1'd0;   //at time 0
   rst = 1'd0; //at time 0
   rst = #2 1'd1; //at time 2
   rst = #5 1'd0; //at time 7
end

always           //generate clock
clk = #3 ~clk; //invert every 3 time units
  
initial begin
$dumpfile("dump.vcd"); //record waveform
$dumpvars(0);            //display signals in all levels
end
  
VVM DUT(clk, rst, a, b, value, done); // instantiate VVM

endmodule // test_VVM

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