Question

I need help writing a test bench for the following Verilog code

module CU(IE, WE, WA, RAE, RAA, RBE, RBA, ALU,
               SH, OE, start, clk, reset, Ng5);
//nG5 denotes (N>5);
   input start, clk, reset;
   output IE, WE, RAE, RBE, OE;
   output [1:0] WA, RAA, RBA, SH;
   output [2:0] ALU;
  
   input wire Ng5;
   reg [1:0] state;
   reg [1:0] nextstate;

   parameter S0 = 3'b000;
   parameter S1 = 3'b001;
   parameter S2 = 3'b010;
   parameter S3 = 3'b011;
  
   initial
       state = S0;
  
   // State register
   always @ (posedge clk)
   begin
       state <= nextstate;
   end
   // NS logic
   always @ (*)
       case(state)
           S0:    if(start) nextstate = S1
                   else nextstate = S0;
           S1:   if(Ng5) nextstate = S3;
                   else nextstate = S2;
           S2: if(reset) nextstate = S0;
                   else nextstate =S2;
           S3:   if(nextstate) nextstate = S0;
                   else nextstate = S3;      
       default: nextstate = S0;
                   endcase
      
       // output logic
   assign IE = state == S1;
   assign WE = (state == S0) || (state == S1);
   assign WA[1] = 0;
   assign WA[0] = state == S1;
   assign RAE = (state == S0) || (state ==S2) ||
                   (state == S3);
   assign RAA[1] = 0;
   assign RAA[0] = 0;
   assign RBE = state == S0;
   assign RBA[1] = 0;
   assign RBA[0] = 0;
   assign ALU[2] = state== S0|| state==S3;
   assign ALU[1] = state == S3;
   assign ALU[0] = state == S0;
   assign SH[1] = 0;
   assign SH[0] = 0;
   assign OE = state == S2 || state == S3;

endmodule