Question

Write a testbench for use in Quartus' ModelSim Altera in verilog for the following code of a 4x16 register:

module regFile4x16
(input clk,
input write,
input [2:0] wrAddr,
input [15:0] wrData,
input [2:0] rdAddrA,
output [15:0] rdDataA,
input [2:0] rdAddrB,
output [15:0] rdDataB);

reg [15:0]    reg0, reg1, reg2, reg3;

assign rdDataA = rdAddrA == 0 ? reg0 :
       rdAddrA == 1 ? reg1 :
       rdAddrA == 2 ? reg2 :
       rdAddrA == 3 ? reg3 : 0;
             
assign rdDataB = rdAddrB == 0 ? reg0 :
       rdAddrB == 1 ? reg1 :
       rdAddrB == 2 ? reg2 :
       rdAddrB == 3 ? reg3 : 0;

always @(posedge clk) begin
if (write)
   case (wrAddr)
   0: begin
   reg0 <= wrData;
   end
   1: begin
   reg1 <= wrData;
   end
   2: begin
   reg2 <= wrData;
   end
   3: begin
   reg3 <= wrData;
   end
   endcase
end
endmodule

Answer 1

//Testbench

`timescale 10 ns / 1 ns

module regFile4x16_tb;

reg clk, write;
reg [2:0] wrAddr;
reg [15:0] wrData;
reg [2:0] rdAddrA, rdAddrB;

wire [15:0] rdDataA, rdDataB;

regFile4x16 uut(clk, write, wrAddr, wrData, rdAddrA, rdDataA, rdAddrB, rdDataB);

initial begin

clk = 1'b0;

rdAddrA = 3'b000;

rdAddrB = 3'b000;

write = 1'b1;

wrAddr = 3'b000;

wrData = 16'hFFFF;

#20;

wrAddr = 3'b001;

wrData = 16'hEEEE;

#20;

wrAddr = 3'b010;

wrData = 16'hDDDD;

#20;

wrAddr = 3'b011;

wrData = 16'hCCCC;

#20;

rdAddrA = 3'b001;

rdAddrB = 3'b011;

#20;

rdAddrA = 3'b010;

rdAddrB = 3'b011;

#20;

rdAddrA = 3'b011;

rdAddrB = 3'b001;

#20;

end

always #10 clk = ~clk;

endmodule

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//modelSim Simulation