Question

Im building a clock using HDL system verilog and I need help implementing this instantiation method. Basically what happens is in the top module ClockCounter, positive clock edges are counted and passed into module timer using instantiation. Once the counter reaches MaxCount (59), a carry is generated which increments the minute clock. Once the minute clock reaches 59, another carry is generated which increments the hour clock. In module timer() below, I need help figuring out what variables in each ClockCounter instantiation need to be declared and what type they need to be declared as in module timer(). On a side note the clock will count in military time.

module ClockCounter(input Clk, Run, Reset, input [7:0] MaxCount,
           output [7:0] Count, output reg Carry);

   always_ff@(posedge Clk or posedge Reset) begin
   if (Reset) begin
       Count <= 0;
       Carry <= 0;
   end
   else
    if (Run)
       if (Count < MaxCount) begin
       Count <= Count + 8'd1;
       Carry <= 0;
       end
   else begin
       Count <= 0;
        Carry <= 1;
   end
    end
endmodule

module timer(//variable declarartions)

ClockCounter SecClk (clk_sec, Run_t, Reset_t, fiftynine, Seconds, Carry_scl);
ClockCounter MinClk (Carry_scl, Run_t|set_min_t, Reset_t, fiftynine, Minutes, Carry_mcl);
ClockCounter HrClk (Carry_Mcl, Run_t,|set_hr_t, Reset_t, twentythree, Hours, Carry_hcl);

endmodule

Answer 1

//I don't understand why set_min_t and set_hr_t is there , except to pause value.

//I have taken these two as ports in top module as you haven't given any information about those. If you need to change in design let me know.

module ClockCounter(input Clk, Run, Reset, input [7:0] MaxCount,
output reg [7:0] Count, output reg Carry);

always_ff@(posedge Clk or posedge Reset) begin
if (Reset) begin
Count <= 0;
Carry <= 0;
end
else
if (Run)
if (Count < MaxCount) begin
Count <= Count + 8'd1;
Carry <= 0;
end
else begin
Count <= 0;
Carry <= 1;
end
end
endmodule


module timer(
//variable declarartions
input clk,Reset_t,Run_t,set_min_t,set_hr_t,
output [7:0]Hours,Minutes,Seconds
);

wire clk_sec,Carry_scl,Carry_mcl,Carry_hcl;
wire [7:0]fiftynine,twentythree;

assign clk_sec = clk;

// Default constant values which will be max count for hours and minutes

assign fiftynine = 59;
assign twentythree = 23;

//Instantiation of clock counter module 3 times for hours,minutes and seconds clock
ClockCounter SecClk (clk_sec, Run_t, Reset_t, fiftynine, Seconds,Carry_scl);
ClockCounter MinClk (Carry_scl, (Run_t|set_min_t), Reset_t, fiftynine, Minutes, Carry_mcl);
ClockCounter HrClk (Carry_mcl, (Run_t|set_hr_t), Reset_t, twentythree, Hours, Carry_hcl);


endmodule

//Testbench
`timescale 1s/100ms
module test;
reg clk,Reset_t,Run_t,set_min_t,set_hr_t;
wire [7:0]Hours,Minutes,Seconds;

always begin
#5 clk = 1'b0;
#5 clk = ~clk;
end

timer TIMER(clk,Reset_t,Run_t,set_min_t,set_hr_t,Hours,Minutes,Seconds);
initial begin
{Reset_t,Run_t,set_min_t,set_hr_t} = 'd0; //Making or initialising all 0's
Reset_t = 1'b1;
@(posedge clk) Reset_t = 1'b0;
Run_t = 1'b1;
#1000000 $finish;
end
endmodule

Wave Default /test/clk /test/Reset t /test/Run t /test/set min t o /test/set hr t o /test/Hours test/Minutes59 ttest/Seconds 59 Now 0000000000 ns 863900000000000 8640000000D0000 ns Cursor 1 1100000000 ns ATranscript ,, !( Wave Objects rocesses rary| sim x