Question

a) Write a Verilog module that implements a 1-bit partial full adder (PFA).

b) Through instantiating the module in a) plus other logic, implement a 4-bit full adder with Verilog.

c) Write a proper test-bench and stimulus, thoroughly test your 4 bit carry lookahead adder.

d) Show a waveform snapshot that indicates you adder can correctly compute 0101 + 1101 and show your results.

Answer 1

(D)..

(A)..you can see simple 1 bit full adder below,

module full_adder(a,b,cin,sum,carry);

input a,b,cin;

output sum,carry;

assign sum=a^b^cin;

assign carry=((a&b)|(b&cin)|(a&cin));

(B)..using this adder we will develop 4 bit carry look ahed adder,

you can see the code of carry look ahed adder below,

module carry_lookahed_addr(a,b,sum_out,carry_out);

input [3:0]a,b;

wire [4:0]cin_w;//it has 4 bit carry pin

output [4:0]sum_out;// result of sum

output carry_out;

wire [3:0]sum;// we have used 3 internal wire for instantiation and calculation of carry generation and propagation

wire [3:0]carry_generate,carry_propagate;

full_adder d1(.a(a[0]),.b(b[0]),.cin(cin_w[0]),.sum(sum[0]),.carry());// for 4 bit adder we have instantiate 1 bit adder 4 times

full_adder d2(.a(a[1]),.b(b[1]),.cin(cin_w[1]),.sum(sum[1]),.carry());

full_adder d3(.a(a[2]),.b(b[2]),.cin(cin_w[2]),.sum(sum[2]),.carry());

full_adder d4(.a(a[3]),.b(b[3]),.cin(cin_w[3]),.sum(sum[3]),.carry());

assign carry_generate[0]=a[0]&b[0];// equation for carry generation C_G=a&b,

assign carry_generate[1]=a[1]&b[1];

assign carry_generate[2]=a[2]&b[2];

assign carry_generate[3]=a[3]&b[3];

assign carry_propagate[0]=a[0]^b[0];

assign carry_propagate[1]=a[1]^b[1];

assign carry_propagate[2]=a[2]^b[2];

assign carry_propagate[3]=a[3]^b[3];

assign cin_w[0] = 0; // no carry input

assign cin_w[1] = carry_generate[0] | (carry_propagate[0] & cin_w[0]);

assign cin_w[2] = carry_generate[1] | (carry_propagate[1] & cin_w[1]);

assign cin_w[3] = carry_generate[2] | (carry_propagate[2] & cin_w[2]);

assign cin_w[4] = carry_generate[3] | (carry_propagate[3] & cin_w[3]);

  

assign sum_out={cin_w[4],sum};

assign carry_out=cin_w[4];

(C).you can see test bench for 4 bit carry look ahed adder

module top;

reg[3:0]a,b;//for test bench input will be reg

wire [4:0]sum_out; //output will be wire

wire carry_out;//output will be wire

carry_lookahed_addr dut(.a(a),.b(b),.sum_out(sum_out),.carry_out(carry_out));//instantiation of 4 bit carry look ahed adder design

initial begin

a=0;

b=0;

#10;

a=4'd14;

b=4'd12;

#10;

a=4'd3;

b=4'd3;

#10;

a=4'd3;

b=4'd5;

#10;

a=4'd11;

b=4'd3;

#10;

a=4'd7;

b=4'd5;

#10;

a=4'd3;

b=4'd4;

#200;

$finish;

end

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