Question

5.4 2um

4-34. Design a negative-edge-triggered flip-flop. The flip flop has three inputs; these are Data, Clock, and Enable. If, at the negative edge of the clock, the enable input equals to 0, then the state at Data input is stored in the flip-flop. If, at the negative edge of clock, Enable is in 1 state, then the current stored value in the flip-flop is held. Design the flip-flop using only SR latches, AND gates, and NOT gates.

Answer 1

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