Question

In the second part of this lab, we will extend our adder to also allow for subtraction of the second number from the first. To implement this, we must take the 2's compliment of the second number and add it to the first. This can be implemented using the circuit shown in Section 4.4.2 of the notes, which is shown again here in Figure 2. B3 A3 B2 A B, A, B, A, -SM 0: Add 1: Subtract CO Fig. 1 Modular design of 4-bit adder/subtractor The circuit has two modes of operation depending on the value of the add/subtract bit. When this bit is zero, which indicates addition, the second number is left unchanged by the XOR gates and the adder simply adds the two numbers as expected. When the add/subtract bit is one, which indicates subtraction, the bits of the first number are inverted by the XOR gates to produce the l's complement. This 1's complement is added to the first number, and the add/subtract bit is fed into the carry-in of the adder to convert the l's complement to 2's complement.

Question:

Part 1:

Answer 1

the Verilog code for the design:

module HA(a,b,s,cout);
input a,b;
output s,cout;
assign s=a^b;
assign cout=a & b;
endmodule

module FA(a,b,cin,s,cout);
input a,b,cin;
output s,cout;
wire s1,c1,c2;
HA h1(a,b,s1,c1);
HA h2(cin,s1,s,c2);
or rrr1(cout,c1,c2);
endmodule

module four_bit_adder(a,b,cin,s,cout);
input [3:0] a,b;
input cin;
output [3:0] s;
output cout;
wire c0,c1,c2;
FA f0(a[0],b[0],cin,s[0],c0);
FA f1(a[1],b[1],c0,s[1],c1);
FA f2(a[2],b[2],c1,s[2],c2);
FA f3(a[3],b[3],c2,s[3],cout);
endmodule

module four_bit_add_Sub(a,b,sub,out,carry);
input [3:0] a,b;
input sub;
output [3:0] out;
output carry;
wire [3:0] b_out;
xor x1(b_out[0],b[0],sub);
xor x2(b_out[1],b[1],sub);
xor x3(b_out[2],b[2],sub);
xor x4(b_out[3],b[3],sub);
  
four_bit_adder f111(a,b_out,sub,out,carry);
endmodule

the incomplete module mentioned is also completed here

module four_bit_add_sub (SW,LEDG);

input [8:0] SW;

output [3:0] LEDG;

wire [3:0] B_ones,sum;

assign B_ones[0]=SW[0] ^ SW[1];

assign B_ones[1]=SW[0]^SW[2];

assign B_ones[2]=SW[0]^SW[3];

assign B_ones[3]=SW[0]^SW[3];

fout_bit_adder(sum,{SW[8:5],B_ones,SW[0]});// since b_ones is the input to adder

assign LEDG=sum;

endmodul