Question

2. In this question, you are asked to design a synthesizable ALU in Verilog. This ALU gets two 9-bit signed inputs (A, B) in 2’s complement format, and a 4-bit select input (S) based on which decides about the operation that should be executed. The output is Q, and you determine the number of bits for Q in order to have a correct answer. What follows shows these operations:

If S=0 Addition (i.e., A+B)

If S=1 Subtraction (A-B)

If S=2 Multiplication (only the least 8 significant bits are shown in output)

If S=3 Shift B to the right A times (and add 0 from right side)

If S=4 Rotate B to the left A times

If S=5 A is ored with B

If S=6 A is anded with B

If S=7 A is nanded with B

If S=8 A is xnored (the logical opposite of XOR, like NAND to AND) with B

If S=9 complement of B is computed

I am confuse here how to addition, subtraction and multiplication

my attempt so far

module ALU(A, B , S, Q);
input [9:0] A;
input [9:0] B;
input [4:0] S;
output reg Q;

always @* begin
case (S)
5'b00000 : Q = A[9:0] + A[9:0] ;
5'b00001 : Q = 0 ;
5'b00010 : Q =
5'b00011 : Q =
5'b00100 : Q = A | B ;
5'b00101 : Q = A & B ;
5'b00110 : Q = A ~&B ;
5'b00111 : Q = A B ;
5'b01000 : Q = A
5'b01001 :
endcase

end
endmodule

Answer 1

// please look for the mistakes u made with the bit vector numbering and also with the output logic

module alu(a,b,out,sel);
input signed [8:0] a,b;// inputs 9 bits each signed
input signed [3:0] sel;// 4 bit select signal signed
output reg signed [8:0] out;// since alu is 8 bit hence output should be 8 bits wide
  
always@(*)
begin
case(sel)
0: out=a+b;
1: out=a-b;
2: out=a*b;
3: out=b>>a;
4: out=b<<a;
5: out=a|b;
6: out=a&b;
7: out=a ~& b;
8: out=a ~^ b;
9:out=~b;
default:out=0;
endcase
end
endmodule