Question

module Lab5(Clock, Ex, Reset, W, S, L, Q);

//Inputs

input Clock, Ex, Reset;

input [1:0] W;

input [2:0] S;

input [3:0] L;

//Outputs

output reg [3:0] Q;

// Inputs for FSM = Clock, Ex, Reset, W           Outputs = S, L

FSM U0 (.Clock(Clock), .Ex(Ex), .Reset(Reset), .W(W), .S(S), .L(L));

// Inputs for BUSR = Clock, Reset, L, S                       Outputs = Q

Behavioral_Universal_Shift_Register U1 (.Clock(Clock), .Reset(Reset), .L(L), .S(S), .Q(Q));

endmodule

How do you use the outputs in FSM file as inputs in the Behavioral_Universal_Shift_Register file? This Verilog code is giving me the error of "10663 Verilog HDL Port Connection error at Lab5.v(23): output or inout port "Q" must be connected to a structureal net expression".

Answer 1

Declare - output reg [3:0] Q; as wire. i.e. output [3:0] Q;

No output from this uut -FSM U0 (.Clock(Clock), .Ex(Ex), .Reset(Reset), .W(W), .S(S), .L(L));