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Instantiate four copies of the mux2_1b in mux2_4b file. Connect the 1-bit muxes (4 mux2_1b instances)...

Instantiate four copies of the mux2_1b in mux2_4b file. Connect the 1-bit muxes (4

mux2_1b instances) with ports of mux2_4b to produce 4-bit wide 2:1 multiplexer. This is

an example of hierarchical design with reusable modules.

The mux2_4b module receives input signals a[3:0], b[3:0], sel, and generates an output

signals y[3:0].

I already have a 2_1bit mux verilog coded out but I am not getting correct results intended by what the question is asking.

//multiplexer using copies of a mux2:1

module mux2_4b(c,d,sel,y);

       input [3:0]c;
       input [3:0]d;
       input sel;
       output reg [3:0]y;
      
      
       mux2 f1(.a(c[0]),.b(d[0]),.sel(sel),.x(y[0]));
       mux2 f2(.a(c[1]),.b(d[1]),.sel(sel),.x(y[1]));
       mux2 f3(.a(c[2]),.b(d[2]),.sel(sel),.x(y[2]));
       mux2 f4(.a(c[3]),.b(d[3]),.sel(sel),.x(y[3]));


       // always @(sel, c , d)
       //       if (sel == 0)
       //   //       y <= c;
           //   else
       //           y <= d;
                      
       endmodule

engineering   Electrical-Engineering   
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