Question

2. Let’s create a module that defines a 4:1 mux by instantiating three 2:1 muxes. Assume the module we are going to instantiate has the interface definition:

module mux2tol (w0,wl,s,f) input w0, wl, s; output f,

(a) First, write the code that would go inside the module defined above.

(b) Now define the interface for your 4:1 mux. You can call the module anything you want and use any variable names you want. But think about how many inputs you’ll need.

(c) Now instantiate three instances of the 2:1 mux defined above and connect the ports correctly to match your interface definition in part (b). Note that you may also need to define a few internal wires.

Answer 1

a) code for the 2to1 mux. Here I am using dataflow modelling.

module mux2to1(w0,w1,s,f);

input w0,w1,s;

output f;

assign f=(s&w0)|((~s)&w1);

endmodule

b) now we have to instantiate the mux4to1 by mux2to1 Note that 4to1 multiplexer contains 4 inputs 2 select lines so total 6 inputs. 1 output. Instantiating the module

module mux4to1(a,b,c,d,s0,s1,z);

input a,b,c,d,s0,s1;

output z;

wire z1,z2;

Here wire z1 and z2 are used to interconnect the mux2to1 instances inside mux 4 to1.

C)

module mux4to1(a,b,c,d,s0,s1,z);

input a,b,c,d,s0,s1;

output z;

wire z1,z2;

mux2to1 m1(a,b,s0,z1);

mux2to1 m2(c,d,s0,z2);

mux2to1 m3(z1,z2,s1,z);

endmodule

Cs Scanned with CamScanner

File Edit View Simulation Window Layout Help 12.00029 Name Value X1:1.998730 us