Question

A computer architect at ARM believes that in one of their system millions of applications run at the same time, but the applications; memory footprints is low in that all of their translations will be cached in TLB, but accessing TLB requires 1 cycle. What would be cache design that you would suggest to him?

Group of answer choices

PIPT

VIPT

VIVT

(All will perform the same)

Answer 1

The cache design cuoul Cache design cuould be VIPI, that I should . suggest to him. VIPT will perform more accusetly. "Intel also use .. a virtual index physical tagged cache, and not Viva on PIPT. : General benefits are o virtual indexing means you can start reading the set from the cache before looking up the frowsalation in the TLB. This means that the common case look up would be done much faster thom a physically idexed cache where you can only lookup the cache after you have the troomsalation, physical tagged allows you to avoid aliasing - both in cases where a single vintial address maps to several physical ones, and multiple virtual adresies map to the same physical line. Both cases may cause loss of coherency in a virtually togged eache and would require complicated mechanisms toro detection