Question

oint each total Implement decade counter in VHDL (counter that counts from 0 to 9). The counter needs to have the following signals: out, enable, reset. a) max pulse reached which has value 1 only when the out is 9. b) Show its block diagram c) Implement VHDcode that connects two 0-9 counters in order to count from 0 to 99. Make sure that you use two counters developed in a). d) Show the block diagram of the implementation in c). e) Let Te and Tsup of the D FF be Ins and 0.25 ns, and the propagation delays of the incrementor. comparator and multiplexer be 5 ns. 3 ns and 0.75 ns respectively. Determine the maximal clock rate of the counter in a). Will we get different maximum clock rate for the circuit implemented in c)? Why? t)

Answer 1

a)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decade is

Port ( reset, clock, enable : in STD_LOGIC;

counter_out : out STD_LOGIC_VECTOR (3 downto 0);

max : out STD_LOGIC);

end decade;

architecture arch of decade is

signal reg : STD_LOGIC_VECTOR (3 downto 0):= "0000";

begin

process (clock, reset, enable)

begin

if (reset = '1') then reg <= "0000";

elsif rising_edge (clock) then

if (enable = '1') then

if (reg = "1001") then

reg <= "0000";

else

reg <= reg + "0001";

end if;

end if;

end if;

end process;

counter_out <= reg;

max <= '1' when (reg = "1001") else '0';

end arch;

Simulation on Xilinx ISIM

(b) and (d)

(c)

We use structural modelling. Here code of part (a) question used as component

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cascaded is
Port ( clock, reset, enable : in STD_LOGIC;
COUNTER_OUT0 : out STD_LOGIC_VECTOR (3 downto 0);
COUNTER_OUT1 : out STD_LOGIC_VECTOR (3 downto 0);
max : out STD_LOGIC);
end cascaded;

architecture Behavioral of cascaded is

component decade is
Port ( reset, clock, enable : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (3 downto 0);
max : out STD_LOGIC);
end component;

signal s0, s1 : std_logic;

begin

U0: decade port map (reset, clock, enable, COUNTER_OUT0, s0);
U1: decade port map (reset, clock, s0, COUNTER_OUT1, s1);

max <= s0 and s1;

end Behavioral;