1- (a) What is the instruction set of a processor architecture? (b) Consider two different processor...
1-
(a) What is the instruction set of a processor architecture?
(b) Consider two different processor architectures X and Y. Briefly explain how the instruction sets of X and Y
compare (are they the same? do they differ?)
(c) Is the size—in bits or bytes—of an instruction part of the ISA?
2-
(a) Assembly language consists of nothing but bits? True False
(b) Machine language consists of nothing but bits? True False
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(a) What is the instruction set of a processor
architecture?
(b) Consider two different processor...
Consider the implemented of two different processors P1, and P2 with the same instruction set architecture...
Consider the implemented of two different processors P1, and P2 with the same instruction set architecture (ISA). P1 has a 2 GHZ clock rate and P2 has a 2.5 GHz clock rate. a. what is the clock cycle for each processor? b. If the CPI for a program A is 2, which processor has the highest performance? c. if the processors P1 execute the program in 2 seconds, find the number of instructions. d. We are trying to reduce the...
How many instructions (different opcodes) can a microprocessor have if the instruction set architecture (ISA) has...
How many instructions (different opcodes) can a microprocessor have if the instruction set architecture (ISA) has following properties: 16-bit word size 3-address instructions 8 registers
please answer all of 5,thank you! QUESTION 1 Choose one that an instruction-set-architecture doesn't define the...
please answer all of 5,thank you!
QUESTION 1 Choose one that an instruction-set-architecture doesn't define the number of general purpose registers the size of the program counter register instructions and their binary encodings instructions and their cycle times QUESTION 2 ADD instruction in the RV321 RISC-V ISA is an arithmetic instruction True False QUESTION 3 Consider the following C code f-g+h+itik If it is compiled for an ISA where an 'ADD' instruction takes two source registers and one output register...
Question 3: ARM Processor a) What is the number of bits in a general-purpose register (e.g., R1) of the ARM Cortex-M4 processor (CPU)? b) What is the number of bits in a memory address for the ARM pr...
Question 3: ARM Processor a) What is the number of bits in a general-purpose register (e.g., R1) of the ARM Cortex-M4 processor (CPU)? b) What is the number of bits in a memory address for the ARM processor architecture? c) What is the number of bits in an assembly instruction for the ARM Thumb-2 instruction set? d) Consider the memory map used with the TM4C123 microcontroller shown below. If the stack is in data memory, what is the initial address...
Assembly Language: Is it TRUE or FALSE: Reduced Instruction Set Computers (RISC) are characterized by: Relatively...
Assembly Language: Is it TRUE or FALSE: Reduced Instruction Set Computers (RISC) are characterized by: Relatively few instructions Relatively few addressing modes Memory access is limited to load and store instructions All operations are done within the registers of the CPU Fixed-length, easily decoded instruction format Relatively large number of registers in the processor A) True B) False
Goals: To learn general-purpose register architectures. To learn encoding an instruction set. Questions: 100 points: (1)...
Goals: To learn general-purpose register architectures. To learn encoding an instruction set. Questions: 100 points: (1) 30 points, (2) 70 points 1. (30 points) The design of MIPS provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List and discuss as many trade-offs as you can that should be considered by instruction set architecture designers examining whether to, and how much to increase the numbers of MIPS registers. 2. [70 points] Consider...
Consider two different implementations of the same instruction set architecture. There are 5 classes of instructions,...
Consider two different implementations of the same instruction set architecture. There are 5 classes of instructions, A, B, C, D, and E. The clock rate and CPI of each class is given in the following table. Machine Clock Rate CPI class A CPI class B CPI class C CPI class D CPI class E P1 1.0 GHz 1 1 2 3 2 P2 1.5 GHz 1 2 3 4 3 What are the performances of P1 and P2 expressed in...
Consider two different implementations of the same instruction set architecture. The instructions can be divided into...
Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CPIs of 2, 4, 3, and 2 and P2 with a clock rate of 3.5 GHz and CPIs of 3, 3, 2, and 3. a. Given a program with a dynamic instruction count of 1.0E8 instructions divided into classes as follows: 30% class...
1. Consider the code sequence: C= A + B D= A-E F= C+ D Assume the...
1. Consider the code sequence: C= A + B D= A-E F= C+ D Assume the values A, B, C, D, E, and F reside in memory. For each Architecture I. Accumulator Architecture II. Memory- Register Architecture III. Register-Register Architecture write the code assuming the instruction codes (opcode) are 8 bits, memory addresses are 32 bits, and register addresses are 6 bits and CPU has 64 Registers; and create a table which specifies: – The execution sequence – The variables...
Consider two different implementations, M1 and M2, of the same instruction set. There are three classes...
Consider two different implementations, M1 and M2, of the same
instruction set. There are three classes of instructions (A, B, and
C) in the instruction set. M1 has a clock rate of 80 MHz and M2 has
a clock rate of 100 MHz. The average number of cycles for each
instruction class and their frequencies (for a typical program) are
as follows:
(a) Calculate the average CPI for each machine, M1, and M2.
(b) Calculate the average MIPS ratings for...
How many instructions (different opcodes) can a microprocessor have if the instruction set architecture (ISA) has following properties: 16-bit word size 3-address instructions 8 registers
please answer all of 5,thank you!
QUESTION 1 Choose one that an instruction-set-architecture doesn't define the number of general purpose registers the size of the program counter register instructions and their binary encodings instructions and their cycle times QUESTION 2 ADD instruction in the RV321 RISC-V ISA is an arithmetic instruction True False QUESTION 3 Consider the following C code f-g+h+itik If it is compiled for an ISA where an 'ADD' instruction takes two source registers and one output register...
Question 3: ARM Processor a) What is the number of bits in a general-purpose register (e.g., R1) of the ARM Cortex-M4 processor (CPU)? b) What is the number of bits in a memory address for the ARM processor architecture? c) What is the number of bits in an assembly instruction for the ARM Thumb-2 instruction set? d) Consider the memory map used with the TM4C123 microcontroller shown below. If the stack is in data memory, what is the initial address...
Goals: To learn general-purpose register architectures. To learn encoding an instruction set. Questions: 100 points: (1) 30 points, (2) 70 points 1. (30 points) The design of MIPS provides for 32 general-purpose registers and 32 floating-point registers. If registers are good, are more registers better? List and discuss as many trade-offs as you can that should be considered by instruction set architecture designers examining whether to, and how much to increase the numbers of MIPS registers. 2. [70 points] Consider...
Consider two different implementations, M1 and M2, of the same
instruction set. There are three classes of instructions (A, B, and
C) in the instruction set. M1 has a clock rate of 80 MHz and M2 has
a clock rate of 100 MHz. The average number of cycles for each
instruction class and their frequencies (for a typical program) are
as follows:
(a) Calculate the average CPI for each machine, M1, and M2.
(b) Calculate the average MIPS ratings for...
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